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ACT5260 64-Bit Superscaler Microprocessor
Features
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Full militarized QED RM5260 microprocessor Dual Issue superscalar QED RISCMarkTM - can issue one integer and one floating-point instruction per cycle microprocessor - can issue one integer and one floating-point instruction per cycle q 100, 133 and 150MHz frequency (200MHz future option) Consult Factory for latest speeds q 260 Dhrystone2.1 MIPS q SPECInt95 4.8. SPECfp95 5.1 High performance system interface compatible with R4600, R4700 and R5000 q 64-bit multiplexed system address/data bus for optimum price/performance up to 100 MHz operating frequency q High performance write protocols maximize uncached write bandwidth q Operates at input system clock multipliers of 2 through 8 q 5V tolerant I/O's q IEEE 1149.1 JTAG boundary scan Integrated on-chip caches - up to 3.2GBps internal data rate q 16KB instruction - 2 way set associative q 16KB data - 2 way set associative q Virtually indexed, physically tagged q Write-back and write-through on per page basis q Pipeline restart on first double for data cache misses Integrated memory management unit q Fully associative joint TLB (shared by I and D translations) q 48 dual entries map 96 pages q Variable page size (4KB to 16MB in 4x increments)
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Embedded supply de-coupling capacitors and Pll filter components High-performance floating point unit - up to 400 MFLOPS q Single cycle repeat rate for common single precision operations and some double precision operations q Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations q Single cycle repeat rate for single precision combined multiply-add operation MIPS IV instruction set q Floating point multiply-add instruction increases performance in signal processing and graphics applications q Conditional moves to reduce branch frequency q Index address modes (register + register) Embedded application enhancements q Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction q I and D cache locking by set q Optional dedicated exception vector for interrupts Fully static CMOS design with power down logic q Standby reduced power mode with WAIT instruction q 5 Watts typical at 3.3V, less than 175 mwatts in Standby 208-lead CQFP, cavity-up package (F17) 208-lead CQFP, inverted footprint (F24), Intended to duplicate the commercial QED footprint (Consult Factory) 179-pin PGA package (Future Product) (P10)
BLOCK DIAGRAM
Phase Lock Loop Data Set A Data Tag A Store Buffer DTLB Physical Data Tag B Instruction Select Sys AD Instruction Set A
Integer Instruction Register Write Buffer Read Buffer Data Set B Instruction Tag B DBus FPIBus Control Tag Floating-point Register File Unpacker/Packer Floating point Control Aux Tag Load Aligner Joint TLB Integer Register File Integer/Address Adder Integer Control Coprocessor 0 DVA System/Memory Control IVA Data TLB Virtual IntIBus Address Buffer Instruction Tag A ITLB Physical Instruction Set B FP Instruction Register
Floating-point MAdd, Add, Sub,Cvt Div, SqRt
Shifter/Store Aligner Logic Unit ABus
PC Incrementer Branch Adder Instruction TLB Virtual
Integer Multiply, Divide Program Counter
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DESCRIPTION:
The ACT5260 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 64-bit system interface. The ACT5260 can issue both an integer and a floating point instruction in the same cycle. The ACT5260 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.
Integer Unit
Like the R5000, the ACT5260 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5260 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5260 datasheet, these instructions are integer multiply-accumulate and 3-operand integer multiply. The ACT5260 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/ divide operations, and the program counter(PC).
HARDWARE OVERVIEW
The ACT5260 offers a high-level of integration targeted at high-performance embedded applications. Some of the key elements of the ACT5260 are briefly described below.
Register File
The ACT5260 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.
Superscalar Dispatch
The ACT5260 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5260 provides unparalleled price/performance in computationally intensive embedded applications.
ALU
The ACT5260 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle
CPU Registers
Like all MIPS ISA processors, the ACT5260 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. For additional Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMarkTM RM5260TM, 64-Bit Superscalar Microprocessor see the latest QED datasheet (Revision 1.1 July 1998).
Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the ACT5260 uses the simple 5-stage pipeline also found in the circuits R4600, R4700, and R5000. In addition to this standard pipeline, the ACT5260 uses an extended seven stage pipeline for floating-point operations. Like the R5000, the ACT5260 does virtual to physical translation in parallel with cache access.
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SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
Absolute Maximum Ratings1
Symbol VTERM Tc TBIAS TSTG IIN IOUT Rating Terminal Voltage with respect to GND Operating Temperature Case Temperature under Bias Storage Temperature DC Input Current DC Output Current Range -0.52 to 4.6 -55 to +125 -55 to +125 -55 to +125 203 50 Units V C C C mA mA
Notes: 1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. VIN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +5.5 Volts. 3. When VIN < 0V or VIN > Vcc. 4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.
Recommended Operating Conditions
Symbol VCC VIH VIL TC Parameter Power Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Case For 133MHz Parts only Minimum +3.135 0.7VCC -0.5 -55 -40 Maximum +3.465 VCC + 0.5 0.2VCC +125 +125 Units V V V C C
DC Characteristics
(VCC = 3.3V 5%; 133MHz parts: Tc =-40C to +125C, All other parts Tc =-55C to +125C) Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Input High Voltage Input Low Voltage Input Current Input Current Input Current Input Capacitance Output Capacitance Sym VOL1 VOH1 VOL2 VOH2 VIH VIL IIN1 IIN2 IIN3 CIN COUT VIN = 0V VIN = VCC VIN = 5.5V IOL = 20 A IOL = 20 A IOL = 4 mA IOL = 4 mA Conditions 100 / 133 / 150MHz Min Vcc - 0.1 2.4 0.7VCC -0.5 -20 -20 -250 Max 0.1 0.4 VCC + 0.5 0.2VCC +20 +20 +250 10 10 Units V V V V V V A A A pF pF
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SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
Power Consumption
Parameter Active Operating Supply Current Symbol ICC1 ICC2 ICC3 Standby Current ISB1 ISB1 Conditions CL = 0pF, No SysAD activity CL = 50pF, R4000 write protocol without FPU operation CL = 50pF, write re-issue or pipelined writes CL = 0pF CL = 50pF 100MHz, 3.3V 133MHz, 3.3V 150MHz, 3.3V Typ5 800 1000 1100 75 75 Max 1550 1750 2000 150 150 Typ5 800 1000 1100 75 75 Max 1550 1750 2000 150 150 Typ5 1000 1150 1250 100 100 Max 1750 1950 2250 175 175 Units mA mA mA mA mA
Notes: 5. Typical integer instruction mix and cache miss rates.
AC Characteristics
(VCC = 3.3V 5%; 133MHz parts: Tc =-40C to +125C, All other parts Tc =-55C to +125C)
Capacitive Load Deration
100 / 133 / 150MHz Symbol CLD Load Derate Parameter Minimum Maximum 2 ns/25pF Units
Clock Parameters
100/133/150MHz Parameter SysClock High SysClock Low SysClock Frequency6 SysClock Period Clock Jitter for SysClock SysClock Rise Time SysClock Fall Time ModeClock Period JTAG Clock Period tSCP tJitterIn tSCRise tSCFall tModeCKP tJTAGCKP Symbol tSCHigh tSCLow Transition < 5ns Transition < 5ns Test Conditions Min 4 4 33 Max 75 30 250 5 5 256*tSCP 4*tSCP ns ns MHz ns ps ns ns ns ns Units
Notes: 6. Operation of the ACT5260 is only guaranteed with the Phase Loop enabled.
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SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
System Interface Parameters7
100MHz Parameter Data Output8 tDO mode14...13 = 00 mode14...13 = 01 (slowest) Data Setup Data Hold tDS tDH tRISE = 5ns tFALL= 5ns Symbol Test Conditions Min mode14...13 = 10 (fastest) mode14...13 = 11 1.0 1.0 1.0 1.0 5.0 2.0 Max 7.0 7.5 8.0 8.5 Min 1.0 1.0 1.0 1.0 5.0 2.0 Max 7.0 7.5 8.0 8.5 Min 1.0 1.0 1.0 1.0 5.0 2.0 Max 7.0 7.5 8.0 8.5 ns ns ns ns ns ns 133MHz 150MHz Units
Notes: 7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal. 8. Capacitive load for all output timing is 50pF.
Boot Time Interface Parameters
100/133/150MHz Parameter Mode Data Setup Mode Data Hold Symbol tDS tDH Test Conditions Min 4 0 Max SysClock cycles SysClock cycles Units
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SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
Package Information - "F17" - CQFP 208 Leads
1.131 (28.727) SQ 1.109 (28.169) SQ
53 52 104 105
.0236 (.51) .0158 (.49)
.010R MIN .010R MIN .015 (.381) .009 (.229) .130 (3.302) MAX 05 .100 (2.540) .080 (2.032) .035 (.889) .025 (.635) .009 (.253) .007 (.178)
1.009 (25.63) .9998 (25.37) 51 Spaces at .0197 (51 Spaces at .50)
Detail "A"
1 156 208 157
Pin 1 Chamfer
Detail "A"
.960 (24.384) SQ REF
.055 (1.397) REF
.115 (2.921) MAX
.005 (.127) .008 (.258)
1.331 (33.807) 1.269 (32.233)
.055 (1.397) .045 (1.143)
Units: Inches (Millimeters)
Note: Pin rotation is opposite of QEDs PQUAD due to cavity-up construction.
Future Package - "P10" - PGA 179 Pins (Advanced)
Bottom View
1 V U T R P N M L K J H G F E D C B A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Side View
.100 BSC
1.700 1.840 BSC 1.880
.018
1.700 BSC 1.840 1.880
Aeroflex Circuit Technology
.050 .221 MAX
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SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
ACT5260 Microprocessor CQFP Pinouts - "F17"
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
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Function Vcc (3.3V) NC NC Vcc (3.3V) Vss SysAD4 SysAD36 SysAD5 SysAD37 Vcc (3.3V) Vss SysAD6 SysAD38 Vcc (3.3V) Vss SysAD7 SysAD39 SysAD8 SysAD40 Vcc (3.3V) Vss SysAD9 SysAD41 Vcc (3.3V) Vss SysAD10 SysAD42 SysAD11 SysAD43 Vcc (3.3V) Vss SysAD12 SysAD44 Vcc (3.3V) Vss SysAD13 SysAD45 SysAD14 SysAD46 Vcc (3.3V) Vss SysAD15 SysAD47 Vcc (3.3V) Vss ModeClock JTDO JTDI JTCK JTMS Vcc (3.3V) Vss
Pin # 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
Function NC NC NC Vcc (3.3V) Vss ModeIn RdRdy* WrRdy* ValidIn* ValidOut* Release* VccP VssP SysClock Vcc (3.3V) Vss Vcc (3.3V) Vss Vcc (3.3V) Vss SysCmd0 SysCmd1 SysCmd2 SysCmd3 Vcc (3.3V) Vss SysCmd4 SysCmd5 Vcc (3.3V) Vss SysCmd6 SysCmd7 SysCmd8 SysCmdP Vcc (3.3V) Vss Vcc (3.3V) Vss Vcc (3.3V) Vss Int0* Int1* Int2* Int3* Int4* Int5* Vcc (3.3V) Vss NC NC NC NC
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Pin # 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Function Vcc (3.3V) NMI* ExtRqst* Reset* ColdReset* VccOK BigEndian Vcc (3.3V) Vss SysAD16 SysAD48 Vcc (3.3V) Vss SysAD17 SysAD49 SysAD18 SysAD50 Vcc (3.3V) Vss SysAD19 SysAD51 Vcc (3.3V) Vss SysAD20 SysAD52 SysAD21 SysAD53 Vcc (3.3V) Vss SysAD22 SysAD54 Vcc (3.3V) Vss SysAD23 SysAD55 SysAD24 SysAD56 Vcc (3.3V) Vss SysAD25 SysAD57 Vcc (3.3V) Vss SysAD26 SysAD58 SysAD27 SysAD59 Vcc (3.3V) Vss NC NC Vss
Pin # 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Function NC NC NC NC Vcc (3.3V) Vss SysAD28 SysAD60 SysAD29 SysAD61 Vcc (3.3V) Vss SysAD30 SysAD62 Vcc (3.3V) Vss SysAD31 SysAD63 SysADC2 SysADC6 Vcc (3.3V) Vss SysADC3 SysADC7 Vcc (3.3V) Vss SysADC0 SysADC4 Vcc (3.3V) Vss SysADC1 SysADC5 SysAD0 SysAD32 Vcc (3.3V) Vss SysAD1 SysAD33 Vcc (3.3V) Vss SysAD2 SysAD34 SysAD3 SysAD35 Vcc (3.3V) Vss NC NC NC NC Vcc (3.3V) Vss
SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Part Number ACT-5260PC-100F17C ACT-5260PC-133F17C ACT-5260PC-150F17C ACT-5260PC-100F17I ACT-5260PC-133F17I ACT-5260PC-150F17I ACT-5260PC-100F17T ACT-5260PC-133F17T ACT-5260PC-150F17T ACT-5260PC-100F17M ACT-5260PC-133F17M ACT-5260PC-150F17M Screening Commercial Temperature (0C to +70C) Commercial Temperature (0C to +70C) Commercial Temperature (0C to +70C) Industrial Temperature (-40C to +85C) Industrial Temperature (-40C to +85C) Industrial Temperature (-40C to +85C) Military Temperature (-55C to +125C) Reduced Military Temperature (-40C to +125C) Military Temperature (-55C to +125C) Military Temperature, Screened* (-55C to +125C) Reduced Military Temperature, Screened* (-40C to +125C) Military Temperature, Screened* (-55C to +125C) Speed (MHz) 100 133 150 100 133 150 100 133 150 100 133 150 Package 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP 208 Lead CQFP
Part Number Breakdown
ACT- 5260 PC - 100 F17 M
Aeroflex Circuit Technology Base Processor Type Cache Style PC = Primary Cache Maximum Pipeline Freq. 100 = 100MHz 133 = 133MHz (Screening: T & M -40C to +125C only) 150 = 150MHz 200 = 200MHZ (Future option) Screening C = Commercial Temp, 0C to +70C I = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C, Screened * Q = MIL-PRF-38534 Compliant/SMD if applicable Package Type & Size Surface Mount Package F17 = 1.120" SQ 208 Lead CQFP F24 = 1.120" SQ Inverted 208 Lead CQFP (Consult Factory) Thru-Hole Package P10 = 1.86"SQ PGA 179 pins with shoulder Future Product
* Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
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SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700

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